The disclosure relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device having a vertical channel arrangement.
The area available for a unit memory cell has decreased with the increased demand for semiconductor memory capacity/density. Due to this decrement of the unit memory cell area, a semiconductor device having a vertical channel has been introduced. That is, the semiconductor device includes a vertical channel arrangement by arranging a source and a drain in a vertical direction in an active area.
FIGS. 1A to 1C are cross-sectional views of a semiconductor device which depict a method of fabricating a semiconductor device having a channel formed in a vertical direction according to the related art.
As shown in FIG. 1A, a plurality of gate hard mask layer patterns 12 are formed on a substrate 11. Pillar heads 13 are formed by etching the substrate using the plurality of gate hard mask layer patterns 12 as an etch barrier.
Then, spacers 14 are formed on sidewalls of the gate hard mask patterns 12 and the pillar heads 13, and pillar necks 15 are formed by etching the substrate 11 using the spacers 14 as the etch barrier. Hereinafter, the pillar head 13 and the pillar neck 15 are referred together as a pillar pattern.
Then, a gate insulation layer 16 and a gate electrode 17 are formed to surround the pillar neck 15. That is, the gate electrode 17 is formed by depositing a conductive layer and performing an etch-back process without an additional mask.
As shown in FIG. 1B, impurities are doped on the substrate 11, and hard mask layer patterns 18 are formed to cover each of the pillar patterns. Here, an oxide layer is formed as the hard mask layer patterns 18.
Then, a trench 22 is formed in the impurity doped substrate 11 using the hard mask layer patterns 18 as an etch barrier, thereby forming a buried bit line 19 by isolating the impurity region.
After forming the buried bit line 19, the hard mask layer patterns 18 are removed.
As shown in FIG. 1C, an isolation layer 20 is formed for insulation between the adjacent buried bit lines 19 and between the buried bit line 19 and a word line. Then, a word line 21 is formed for connecting the gate electrodes 17.
By forming the word line 21, the fabrication of the semiconductor device having a vertical channel arrangement is completed.
However, the fabricated semiconductor device according to the related art tends to suffer from following problems.
At first, it is required to form the gate hard mask layer pattern 12 to be relatively thick, for example, about 1500 to 2000 Å, because a great portion of the gate hard mask layer pattern 12 is lost in the etch-back process of forming the gate electrode 17. Therefore, the pillar pattern may become bent because a relatively large weight is applied to the pillar neck 15, which is relatively narrow, while forming the pillar neck 15 as shown in FIG. 1A.
Secondly, it becomes harder to isolate the impurity region as a space between pillar patterns gets smaller. That is, the pillar pattern may be exposed because a portion of the spacer 14 is lost while forming the trench 22 as shown in FIG. 1B. This is caused because the etch selectivity of the hard mask layer pattern 18 is not suited to an etchant gas used for etching the substrate 11. That is to say, while etching the substrate 11, the hard mask layer pattern 18 and the sidewall passivation layer 14, which are formed of an oxide layer, are excessively removed while etching the substrate 11.
Thirdly, the word line 21 may be shorted by the pillar pattern as shown in FIG. 2 which is a plan view of FIG. 1C. Here, the adjacent word lines 21 are connected through the gate electrode. Since a width W10 of the gate electrode 17 is small, the resistance of the word line 21 increases. In general, resistance is in inverse proportion to an area.
Therefore, it has been required to develop a new technology which can overcome the fabrication problems associated with the semiconductor device having the vertical channel according to the related art.